(1) Field of the Invention
The present invention relates to a technique for preventing an increase of clock skew caused by the deterioration of a plurality of logic blocks over time.
(2) Description of Related Art
In a synchronous design method that has been popularly used in an LSI (Large Scale Integration) design in recent years, a clock signal for control is supplied to, for example, state registers, at the same timing. In an actual LSI, the amount of delay of the clock signal caused between a clock generation source and a register is different between each of the registers, depending on a difference in the configuration of a clock supply circuit. Note that the difference of the amount of delay between devices such as the registers is referred to as clock skew.
When more than a predetermined amount of the clock skew occurs, an error occurs, for example, in the transmission and reception of data between the registers, resulting in the LSI failing to operate properly. Therefore, in general, when more than a predetermined amount of clock skew occurs, a delay device for balancing the clock skew between the registers is inserted upon designing, so as to avoid the operation failure of the LSI that is caused by the clock skew.
Also provided is a technique for preventing the occurrence of the clock skew by providing the LSI with (i) a clock line that is for supplying a clock signal to logic blocks, and that is independent from a line connecting the logic blocks, and (ii) a clock control unit for dynamically switching between the supply and cutoff of the clock signal to/from each of the logic blocks (see Patent Document 1, for example).
However, transistors included in the LSI, especially a P-channel MOS transistor, deteriorate over time due to NBTI (Negative Bias Temperature Instability), HCI (Hot Carrier Injection) and such. Assume here that a gated clock technique, a power cutoff technique, or the like, is applied to the LSI, so as to save the power consumed by the LSI. In this case, when the LSI continues to be used, the operation time of each transistor becomes different, and the deterioration degree of each transistor also becomes different due to NBTI and HCI. A difference in deterioration degree is a cause for the occurrence of the clock skew. However, the deterioration of transistors over time is not taken into consideration in the above-described technique. Therefore, with the above-described technique, it is impossible to prevent the operation failure of LSIs due to the clock skew that is caused by the deterioration of transistors over time.
As a technique for suppressing the clock skew caused by the deterioration of transistors over time, a technique is proposed that is for equalizing the deterioration of transistors over time, by controlling the termination of the operation of a flip flop. This control is performed by appropriately selecting (i) a case where the control is performed by fixing the control clock signal to a high level, and (ii) a case where the control is performed by fixing the control clock signal to a low level (see Patent Document 2, for example).    Patent Document 1: Japanese Patent Application Publication No. 2003-174358 (Page 10, FIG. 1); and    Patent Document 2: Japanese Patent Application Publication No. 2006-211494 (Page 18, FIG. 1).